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| 2.5 CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch ADG787 FEATURES USB 1.1 signal switching compliant -3 dB bandwidth, 150 MHz Tiny 10-lead LFCSP and MSOP packages, 10-ball WLCSP package Single-supply 1.8 V to 5.5 V operation Low on resistance 2.5 typical 3.45 maximum at 85C Typical power consumption: <0.1 W FUNCTIONAL BLOCK DIAGRAM ADG787 S1A D1 S1B IN1 IN2 S2A D2 S2B SWITCHES SHOWN FOR A LOGIC 0 INPUT 05250-001 APPLICATIONS USB 1.1 signal switching circuits Cellular phones PDAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems Figure 1. GENERAL DESCRIPTION The ADG787 is a low voltage, CMOS device that contains two independently selectable single-pole, double-throw (SPDT) switches. It is designed as a general analog-to-digital switch and can also be used for routing USB 1.1 signals. This device offers low on resistance of typically 2.5 , making the part an attractive solution for applications that require low distortion through the switch. The ADG787 comes in a 10-ball WLCSP, a tiny 10-lead LFCSP, and a tiny 10-lead MSOP. These packages make the ADG787 the ideal solution for space-constrained applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG787 exhibits break-before-make switching action. 1 MASK: FS (12Mbps) 20.0ns/DIV VIN = 3V p-p TA = 25C Figure 2. Eye Pattern; 12 Mbps, VDD = 4.2 V, PRBS 31 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. 05250-032 ADG787 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configurations and Function Descriptions ............................6 Truth Table .....................................................................................6 Typical Performance Characteristics ..............................................7 Test Circuits ................................................................................ 11 Terminology .................................................................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 15 REVISION HISTORY 5/06--Rev. 0 to Rev. A Updated Formatting ...........................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 3............................................................................ 5 Changes to Ordering Guide .......................................................... 15 1/05--Revision 0: Initial Version Rev. A | Page 2 of 16 ADG787 SPECIFICATIONS VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON tOFF Propagation Delay Skew, tSKEW Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk +25C B Version 1 0 to VDD 2.5 3 0.02 0.65 0.8 0.05 0.05 2.0 0.8 0.005 0.1 2.5 13 19 3 5 0.06 10 5 14 -63 -110 -63 Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 0.03 -0.2 145 16 40 0.005 1 1 2 Unit V typ max typ max typ max nA typ nA typ V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ % dB typ MHz typ pF typ pF typ A typ A max Test Conditions/Comments 3.45 0.1 0.95 VDD = 4.2 V, VS = 0 V to VDD, IS = 10 mA See Figure 28 VDD = 4.2 V, VS = 3.5 V, IS = 10 mA VDD = 4.2 V, VS = 0 V to VDD IS = 10 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 29 VS = VD = 1 V or 4.5 V; see Figure 30 VIN = VINL or VINH 22 6 0.15 RL = 50 , CL = 35 pF VS = 3 V; see Figure 31 RL = 50 , CL = 35 pF VS = 3 V; see Figure 31 CL = 50 pF; VS = 3 V RL = 50 , CL = 35 pF VS1 = VS2 = 3 V; see Figure 32 VD = 1 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 S1A to S2A/S1B to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 36 RL = 32 , f = 20 Hz to 20 kHz, VS = 2 V p-p RL = 50 , CL = 5 pF; see Figure 36 RL = 50 , CL = 5 pF; see Figure 36 VDD = 5.5 V Digital inputs = 0 V or 5.5 V Temperature ranges: B version: -40C to +85C for the MSOP and LFCSP packages, and -25C to +85C for the WLCSP package. Guaranteed by design, not production tested. Rev. A | Page 3 of 16 ADG787 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON tOFF Propagation Delay Skew, tSKEW Break-Before-Make Time Delay (tBBM) Charge Injection Off Isolation Channel-to-Channel Crosstalk +25C B Version 1 Unit V typ max typ max typ max nA typ nA typ 1.3 0.8 0.005 0.1 2 18 30 4 6 0.04 15 5 10 -63 -110 -63 Total Harmonic Distortion (THD + N) Insertion Loss -3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 0.07 -0.24 145 16 40 0.005 1 1 2 Test Conditions/Comments 4 5.75 0.07 0.3 1.6 2.3 0.01 0.01 6 0.35 2.6 VDD = 2.7 V, VS = 0 V to VDD IS = 10 mA; see Figure 28 VDD = 2.7 V, VS = 1.5 V IS = 10 mA VDD = 2.7 V, VS = 0 V to VDD IS = 10 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 29 VS = VD = 0.6 V or 3.3 V; see Figure 30 V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ % dB typ MHz typ pF typ pF typ A typ A max VIN = VINL or VINH 35 7 0.12 RL = 50 , CL = 35 pF VS = 1.5 V; see Figure 31 RL = 50 , CL = 35 pF VS = 1.5 V; see Figure 31 CL = 50 pF; VS = 1.5 V RL = 50 , CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 32 VD = 1.25 V, RS = 0 , CL = 1 nF; see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 34 S1A to S2A/S1B to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 35 RL = 32 , f = 20 Hz to 20 kHz, VS = 1.5 V p-p RL = 50 , CL = 5 pF; see Figure 36 RL = 50 , CL = 5 pF; see Figure 36 VDD = 3.6 V Digital inputs = 0 V or 3.6 V Temperature range: B version: -40C to +85C for the MSOP and LFCSP packages, and -25C to +85C for the WLCSP package. Guaranteed by design, not production tested. Rev. A | Page 4 of 16 ADG787 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Inputs 1 , Digital Inputs Rating -0.3 V to +6 V -0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) 300 mA 200 mA (pulsed at 1 ms, 10% duty cycle max) 100 mA 80 mA Peak Current, S or D 5 V Operation 3.3 V Operation Continuous Current, S or D 5 V Operation 3.3 V Operation Operating Temperature Range Extended Industrial (B Version) MSOP and LFCSP packages Industrial (B version) WLCSP package Storage Temperature Range Junction Temperature WLCSP Package (4-Layer Board) JA Thermal Impedance LFCSP Package (4-Layer Board) JA Thermal Impedance MSOP Package (4-Layer Board) JA Thermal Impedance JC Thermal Impedance Lead-Free Temperature Soldering IR Reflow, Peak Temperature Peak Temperature Time at Peak Temperature 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. -40C to +85C -25C to +85C -65C to +150C 150C 120C/W 61C/W 142C/W 43.7C/W 260(+0/-5)C 10 sec to 40 sec Overvoltages at the IN, S, or D pins are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 16 ADG787 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS a 1 S1B GND S2B VDD 1 S1A 2 10 b c S2A D2 2 IN1 3 D1 05250-002 IN2 D2 S2A 05250-003 ADG787 9 D1 3 8 IN2 TOP VIEW IN1 4 (Not to Scale) 7 S2B S1B 5 6 4 S1A VDD GND Figure 3. 10-Lead LFCSP and 10-lead MSOP Pin Configuration TOP VIEW (BALLS AT THE BOTTOM) Figure 4. 10-Ball WLCSP Pin Configuration Table 4. 10-Lead LFCSP/MSOP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VDD S1A D1 IN1 S1B GND S2B IN2 D2 S2A Description Most Positive Power Supply Potential. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Source Terminal. May be an input or output. Ground (0 V) Reference. Source Terminal. May be an input or output. Logic Control Input. Drain Terminal. May be an input or output. Source Terminal. May be an input or output. Table 5. 10-Lead WLCSP Pin Function Descriptions Ball Location 1a 1b 1c 2a 2c 3a 3c 4a 4b 4c Mnemonic S1B GND S2B IN1 IN2 D1 D2 S1A VDD S2A Description Source Terminal. May be an input or output. Ground (0 V) Reference. Source Terminal. May be an input or output. Source Terminal. May be an input or output. Logic Control Input. Drain Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Most Positive Power Supply Potential. Source Terminal. May be an input or output. TRUTH TABLE Table 6. Logic (IN1/IN2) 0 1 Switch 1A/2A Off On Switch 1B/2B On Off Rev. A | Page 6 of 16 ADG787 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 VDD = 4.5V 2.5 VDD = 4.2V ON RESISTANCE (W) 3.5 TA = 25C IDS = 10mA VDD = 4.2V IDS = 10mA 3.0 TA = +85C ON RESISTANCE (W) 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 SIGNAL RANGE 3.0 3.5 4.0 2.0 VDD = 5V 1.5 VDD = 5.5V TA = +25C TA = -40C 1.0 0.5 05250-004 0 0 1 2 3 SIGNAL RANGE 4 5 Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 4.2 V 5.0 TA = 25C 4.5 IDS = 10mA VDD = 2.7V 4.0 ON RESISTANCE (W) ON RESISTANCE (W) 5.0 4.5 4.0 VDD = 3V 3.5 3.0 2.5 2.0 1.5 1.0 05250-005 VDD = 3V IDS = 10mA TA = +85C 3.5 3.0 2.5 VDD = 3.3V 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 SIGNAL RANGE 3.0 3.5 4.0 VDD = 3.6V TA = +25C TA = -40C 0.5 0 0 0.5 1.0 1.5 2.0 SIGNAL RANGE 2.5 3.0 Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V 3.0 VDD = 5V IDS = 10mA 2.5 TA = +85C ON RESISTANCE (W) Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V 2.0 1.5 1.0 IS, ID (ON) CURRENT (nA) 2.0 0.5 0 -0.5 TA = +25C 1.5 TA = -40C 1.0 IS (OFF) -1.0 0.5 05250-006 05250-040 -1.5 -2.0 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 0 0 0.5 1.0 1.5 2.0 2.5 3.0 SIGNAL RANGE 3.5 4.0 4.5 5.0 Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V Figure 10. Leakage Current vs. Temperature, VDD = 5.5 V Rev. A | Page 7 of 16 05250-008 05250-007 ADG787 2.0 1.5 25 30 TA = 25C 1.0 IS (OFF) CURRENT (nA) 20 0.5 VDD = 3V TIME (ns) 0 -0.5 IS, ID (ON) -1.0 15 TON VDD = 5V 10 TOFF 5 05250-041 VDD = 3V 05250-013 -1.5 -2.0 0 10 20 30 40 50 60 TEMPERATURE (C) 70 80 VDD = 5V 0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 Figure 11. Leakage Current vs. Temperature, VDD = 3.3 V 2.0 1.8 LOGIC THRESHOLD POINT (V) Figure 14. tON/tOFF Time vs. Temperature 0 -1 -2 ATTENUATION (dB) 1.6 1.4 1.2 VIN RISING 1.0 0.8 0.6 0.4 0.2 0 1.5 VIN FALLING VDD = 3V/4.2V/5V TA = 25C -3 -4 -5 -6 05250-014 05250-011 -7 -8 100 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE VDD (V) 5.0 5.5 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G Figure 12. Threshold Voltage vs. Supply 25 TA = 25C 20 VDD = 5V Figure 15. Bandwidth 0 VDD = 3V/4.2V/5V TA = 25C -20 ATTENUATION (dB) 05250-012 -40 QINJ (pC) 15 VDD = 3V 10 -60 -80 5 -100 05250-015 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VD (V) 3.5 4.0 4.5 5.0 -120 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G Figure 13. Charge Injection vs. Source Voltage Figure 16. Off Isolation vs. Frequency Rev. A | Page 8 of 16 ADG787 0 VDD = 3V/4.2V/5V TA = 25C -20 2.5 3.0 INPUT RISE/FALL TIME = 15ns TA = 25C ATTENUATION (dB) -40 DELAY (ns) 2.0 S1A TO S1B -60 S1A TO S2A -80 1.5 1.0 RISE DELAY -100 05250-030 0.5 FALL DELAY 0 2.7 3.2 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 05250-044 -120 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G Figure 17. Crosstalk vs. Frequency 0 2.0 1.8 1.6 1.4 DELAY (ns) Figure 20. Rise/Fall Time Delay vs. Supply Voltage -20 VDD = 3V/4.2V/5V TA = 25C NO SUPPLY DECOUPLING INPUT RISE/FALL TIME = 15ns VDD = 4.2V -40 PSRR (dB) 1.2 1.0 RISE DELAY 0.8 0.6 0.4 FALL DELAY 05250-045 -60 -80 -100 05250-031 0.2 0 -40 -120 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G -15 10 35 TEMPERATURE (C) 60 85 Figure 18. AC Power Supply Rejection Ratio (PSRR) 0.10 0.09 0.08 0.07 THD+N (%) Figure 21. Rise/Fall Time Delay vs. Temperature 2.0 INPUT RISE/FALL TIME = 15ns TA = 25C VDD = 3V, VS = 2V p-p MISMATCH (ns) 05250-043 1.5 0.06 0.05 0.04 0.03 0.02 0.01 0 10 VDD = 5V, VS = 2V p-p 1.0 0.5 05250-046 100 1k FREQUENCY (Hz) 10k 100k 0 2.5 3.0 3.5 4.0 SUPPLY (V) 4.5 5.0 5.5 Figure 19. Total Harmonic Distortion + Noise Figure 22. Rise-Time-to-Fall-Time Mismatch vs. Supply Voltage Rev. A | Page 9 of 16 ADG787 1.2 INPUT RISE/FALL TIME = 15ns VDD = 4.2V 1.0 MASK: FS (12Mbps) MISMATCH (ns) 0.8 0.6 0.4 1 0.2 05250-047 0 -40 -15 10 35 TEMPERATURE (C) 60 85 20.0ns/DIV 2.5GS/s 400ps/pt Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature 300 INPUT RISE/FALL TIME = 15ns TA = 25C 250 Figure 26. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = 85C, PRBS 31 MASK: FS (12Mbps) TPROP SKEW (ps) 200 150 100 1 50 05250-048 0 2.5 3.0 3.5 4.0 SUPPLY (V) 4.5 5.0 5.5 20.0ns/DIV 2.5GS/s 400ps/pt Figure 24. Propagation Delay Skew (tSKEW) vs. Supply Voltage 200 INPUT RISE/FALL TIME = 15ns 180 VDD = 4.2V 160 140 TSKEW (ps) Figure 27. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = -40C, PRBS 31 120 100 80 60 40 20 0 -40 05250-049 -15 10 35 TEMPERATURE (C) 60 85 Figure 25. Propagation Delay Skew (tSKEW) vs. Temperature Rev. A | Page 10 of 16 05250-034 05250-033 ADG787 TEST CIRCUITS IDS IS (OFF) A S D ID (OFF) A VD 05250-017 V1 VS S D Figure 29. Off Leakage VS RON = V1/IDS 05250-016 Figure 28. On Resistance ID (ON) VD 05250-018 NC S D A Figure 30. On Leakage VDD 0.1F VDD VS S1B S1A D RL 50 GND VOUT CL 35pF VOUT VIN 50% 50% IN 90% 90% 05250-019 tON tOFF Figure 31. Switching Times, tON, tOFF VDD 0.1F VIN VDD VS S1B S1A D RL IN GND 50 VOUT VOUT CL 35pF 0V 50% 50% 80% 80% tBBM tBBM 05250-020 Figure 32. Break-Before-Make Time Delay, tBBM VDD SW ON S1B VS IN GND D S1A 1nF VOUT VOUT 05250-021 SW OFF VIN NC VOUT QINJ = CL VOUT Figure 33. Charge Injection Rev. A | Page 11 of 16 ADG787 VDD 0.1F NETWORK ANALYZER 50 VS 0.1F VDD VDD VDD NETWORK ANALYZER 50 VS NC S1B D S1A 50 S1B S1A D 05250-022 GND GND OFF ISOLATION = 20 LOG VOUT VS INSERTION LOSS = 20 LOG VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 34. Off Isolation VDD 0.1F NETWORK ANALYZER VOUT 50 Figure 36. Bandwidth S2A S2B S1A S1B D2 NC VDD VOUT S1A RL 50 50 VS GND D1 NC 50 S1B D 50 RL 50 VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG 05250-023 VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VOUT VS Figure 37. Channel-to-Channel Crosstalk (S1A to S2A) Figure 35. Channel-to-Channel Crosstalk (S1A to S1B) Rev. A | Page 12 of 16 05250-025 05250-024 RL 50 VOUT RL 50 VOUT ADG787 TERMINOLOGY IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between D and S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. RON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID (OFF) Drain leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD (OFF) Off switch drain capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. tBBM On or off time measured between the 80% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. -3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus noise of a signal, to the fundamental. TSKEW The measure of the variation in propagation delay between each channel. Rise Time Delay The rise time of a signal is a measure of the time for the signal to rise from 10% of the ON level to 90% of the ON level. Rise time delay is the difference between the rise time, measured at the input, and the rise time, measured at the output. Fall Time Delay The fall time of a signal is a measure of the time for the signal to fall from 90% of the ON level to 10% of the ON level. Fall time delay is the difference between the fall time, measured at the input, and the fall time, measured at the output. Rise-Time-to-Fall-Time Mismatch This is the absolute value between the variation in the fall time and the rise time, measured at the output. Rev. A | Page 13 of 16 ADG787 OUTLINE DIMENSIONS INDEX AREA 3.00 BSC SQ 10 PIN 1 INDICATOR 1 1.50 BCS SQ TOP VIEW 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 2.48 2.38 2.23 5 6 0.80 0.75 0.70 SEATING PLANE 0.80 MAX 0.55 TYP SIDE VIEW 0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF 1.74 1.64 1.49 0.30 0.23 0.18 Figure 38. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 3.10 3.00 2.90 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 0.33 0.17 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA 1.10 MAX 8 0 0.80 0.60 0.40 10 6 5.15 4.90 4.65 1 5 SEATING PLANE 0.23 0.08 Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. A | Page 14 of 16 ADG787 1.56 1.50 1.44 0.63 0.57 0.51 SEATING PLANE 0.36 0.32 0.28 2.06 2.00 1.94 0.50 BSC BALL PITCH C B A 1 BALL 1 IDENTIFIER 2 3 4 TOP VIEW (BALL SIDE DOWN) Figure 40. 10-Ball Wafer Level Chip Scale Package [WLCSP] (CB-10) Dimensions shown in millimeters ORDERING GUIDE Model ADG787BRMZ 2 ADG787BRMZ-500RL72 ADG787BRMZ-REEL2 ADG787BCBZ-500RL72 ADG787BCBZ-REEL2 ADG787BCPZ-500RL72 ADG787BCPZ-REEL2 1 2 111105-0 0.26 0.22 0.18 0.11 0.09 0.07 BOTTOM VIEW (BALL SIDE UP) Temperature Range -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Ball Wafer Level Chip Scale Package (WLCSP) 10-Ball Wafer Level Chip Scale Package (WLCSP) 10-Lead Lead Frame Chip Scale Package (LFCSP_WD) 10-Lead Lead Frame Chip Scale Package (LFCSP_WD) Package Option RM-10 RM-10 RM-10 CB-10 CB-10 CP-10-9 CP-10-9 Branding 1 SM1 SM1 SM1 S04 S04 SM1 SM1 Due to space constraints, branding on this package is limited to three characters. Z = Pb-free part. Rev. A | Page 15 of 16 ADG787 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05250-0-5/06(A) Rev. A | Page 16 of 16 |
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